FinFET Technology Introduction

FinFET is a new complementary metal oxide semiconductor (CMOS) transistor, an innovative design derived from the traditional standard transistor-“Field Effect Transistor”.

The traditional transistor structure is flat, so it can only control the on and off of the circuit on one side of the gate. However, in the FinFET architecture, the gate is designed as a fork-shaped 3D architecture similar to a fish fin, which can control the on and off of the circuit on both sides of the circuit. This fork-shaped 3D architecture can not only improve circuit control and reduce leakage current, but also greatly reduce the gate length of the transistor.

The first to use the

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was Intel. They used the FinFET process on the 22nm third-generation Core processor, and then major semiconductor manufacturers began to switch to the FinFET process, including TSMC 16nm, 10nm, Samsung 14nm, 10nm and GlobalFoundries 14nm. However, the limit of the FinFET process is the 7nm process. The first generation of the 7nm process will continue to use the FinFET process, but then it will need to rely on the extreme ultraviolet lithography machine.

The aforementioned FinFET can be understood as a three-dimensional transistor. The traditional planar transistor uses the FD-SOI process. Although the FinFET process has occupied the attention of most people in recent years, the FD-SOI process is still very important. If the FinFET process core FD-SOI achieves the same performance, the FD-SOI process is relatively simple in the manufacturing process, but the SOI substrate is slightly more expensive, while the FinFET process is more complex, but the price of the substrate is cheaper. The actual manufacturing cost of the people is not much different.

As mentioned earlier, the FinFET manufacturing process is very complicated. Intel’s Mark Bohl talked about FinFET technology in an interview in 2016 and mentioned that Intel will continue to use the SADP (Self-Aligned Double Patterning) process. Among them, Double Patterning is the current mainstream FinFET manufacturing process. Its principle is to first pattern a batch of 80nm precision patterns, and then interleave a batch of 80nm precision patterns; after two photolithography, the precision can be increased to 40nm.

The future of FinFET process

Technology node is an important criterion for measuring semiconductor technology, but it is not absolute. Whether it is TSMC or Samsung Semiconductor, the most profitable is not the most advanced technology, but the relatively mature technology node. For IC design manufacturers, solutions and technology nodes that balance cost, performance, and demand are the most important. A company is not a philanthropist. It also needs to consider the issue of profitability. Many chips choose when the product performance is sufficient. The most suitable manufacturing process can enhance market competitiveness and expand market share.

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